In the field of communications, ongoing research and development concerns master clock signal distribution and content transport synchronization.
In communications networks, a signal transport delay is incurred when content is conveyed over communications links between communications network nodes. Particularly as content is being conveyed at high bit rates, the ability of communications network nodes to synchronize content transport is diminished: on one hand, due to very short bit transmission time periods at high transport rates, and on the other hand, due to master clock signal source instabilities.
As content transport over communications networks encompassing the Earth incur signal transport delays in the order of seconds, synchronization to an absolute clock signal is hard to achieve and ensure. Attempts have been made towards this end including proposing the use of Global Positioning System (GPS) signals as a master clock signal reference. However, there are no assurances that GPS signals can be received without fail at all times under all conditions.
In the absence of absolute clock signal synchronization, signal synchronization becomes very important. The absence of signal synchronization in conveying content leads to an unbound signal skew introducing further content transport delays and overheads. The absence of signal synchronization in conveying content in the communications infrastructure also leads to an uncontrollable signal transmission and reception jitter which may put detrimental short high demands on storage at intermediary nodes in transport paths. The exemplary uncontrollable jitter and the unbound signal skew mentioned herein above are but a few of the effects typically experienced.
Towards achieving synchronization, clock standards such as Cesium clocks are typically employed to provide master clock signals. Cesium clock generated master clock signals are distributed to individual network nodes in communications networks via designated interconnecting links. While redundancy is a requirement, Cesium clock sources are expensive and if too many are used in a communications network, the synchronization of the multiple Cesium clocks becomes the stumbling block. As network nodes are designed to be multiply and redundantly interconnected in communications networks, it would be impossible to ensure that the content transport paths follow master clock signal distribution paths. Nor can it be ensured that master clock signal distribution paths follow content transport paths. Therefore, inevitably, active synchronization must be performed at each network node in a communications network.
With multiple master clocks in a communications network, multiple master clock signals are typically received at each network node. Therefore active signal synchronization at each network node must include selecting which master clock signal received to be used to phase align content conveyance thereto. Being able to select between multiple sources is desired as master clock signal sources may fail, become unreliable, or at times need servicing; and/or as the clock signal distribution infrastructure may experience failure. In accordance with various interconnectivity standards, at least two master clock signals must be provided to each network node in a communications network: one being designated as the primary master clock signal to which content transport is actively synchronized to, and the other designated as the secondary standby master clock signal to which content transport is to be synchronized to should the primary master clock signal be unavailable or experience degradation.
Take for example a typical single-shelf network node implementation, the single-shelf network node typically has a backplane design which includes a switching fabric with interface card connectors for interfacing with line cards having physical ports thereon. Communications links connect directly to the physical ports. An exemplary Bellcore Stratum-3 compliant 8 kHz System SYNChronization signal (SSYNC), is generated by a System Synchronization Unit (SSU) at each network node. The generated Bellcore Stratum-3 compliant 8 kHz SSYNC signal is frequency locked and phase locked to a selected, externally generated, master clock signal (External SYNChronization signal (ESYNC)) received via one of the physical ports of the single shelf network node. The frequency-locked phase-locked SSYNC signal is subsequently distributed to each line card associated with the single shelf network node for use in conveying content. For the purpose of ESYNC signal collection and SSYNC signal distribution, the backplane design includes special interface card special traces thereon and connector pins, to collect and distribute analog clock signals within the single shelf network node.
Recent developments in the art include:
Prior art U.S. Pat. No. 5,910,753 entitled “Direct Digital Phase Synthesis” which issued on Jun. 8th, 1999 to Bogdan describes the controlled generation of clock signals for telecommunications applications in a single shelf network node from a control voltage signal.
In a prior art U.S. patent application Ser. No. 10/087,521 entitled “Direct Digital Synthesizer Phase Locked Loop” published on Dec. 5th, 2002, O'Leary et al. describe an exemplary direct digital phase locked loop implementation (DPLL) having a numerically controlled oscillator employed in clock generation in a shelf controller of a single shelf network node system implementation. The DPLL synchronizes the system clock to a selected reference clock signal from a shelf element such as an interface card.
A co-assigned prior art U.S. Pat. No. 5,638,410 entitled “Method and System for Aligning the Phase of High Speed Clocks in Telecommunications Systems” which issued on Jun. 10th, 1997 to Kuddes describes the use of a digital delay line to phase align standby and primary clocks to minimize phase-related effects of a clock switchover in a single shelf telecommunications system should the primary clock experience a failure.
The continued increasing demand for higher content transport bandwidth has led to multi-shelf network node designs. As a side effect, the issues related to content transport synchronization and clock signal distribution in communications networks have re-emerged in respect of multi-shelf network node design and implementation. Known solutions employed in single-shelf network node systems cannot be employed in respect of multi-shelf network node systems largely because multi-shelf network node designs are optimized for content transport:
Making reference to FIG. 1, a multi-shelf network node system 100 includes a control shelf 102, a switching shelf 104, and multiple peripheral shelves 106. The peripheral shelves 106 primarily exchange content with the communication network(s) in which the multi-shelf network node 100 participates. The control shelf 102 can be employed exclusively for content transport control and may also participate in content transport.
From the point of view of content switching, the shelves of the multi-shelf system 100 have a star interconnection architecture with the switching shelf 104 as the root node. The switching shelf 104 includes a master switching fabric which switches all traffic between the peripheral shelves 106 (including the control shelf 102 if the control shelf 102 has line cards 118 installed therein). Each peripheral shelf 106 has a Fabric Card (FC) 108 to which all inter-shelf traffic is multiplexed and from which all inter-shelf traffic is demultiplexed. A high bandwidth data link 110, typically an optical fiber trunk, conveys content between at least one fabric card 108 at a peripheral shelf 106(/102) and at least one Switch Access Card (SAC) 114 at the switching shelf 104. Typically little else is provisioned between the peripheral shelves 106(/102) and the switching shelf 104 by design, as data transport optimizations are sought.
From the point of view of control, the shelves of the multi-shelf system 100 have a star interconnection architecture with the control shelf 102 as the root node. The control shelf 102 includes a backplane and control cards 112 providing control layer services to the entire multi-shelf network node system 100. Control Services Links (CSL) 116 convey control information between the control card 112 at the control shelf 102, and a corresponding shelf controller card 115 at each peripheral shelf 106.
It is understood that the entire multi-shelf system interconnectivity infrastructure is redundant. While redundant shelf controller, control, and fabric cards are shown in FIG. 1, redundant links have been omitted from FIG. 1 to simplify the diagram.
In order to achieve high levels of throughput at the multi-shelf network node system 100, the peripheral shelves 106(/102) are optimized for content switching and access to the switching shelf 104. Therefore, control services links 116 typically have low bandwidths when compared with the data links 110. Whereas the data links 110 typically include plain optical links, the control services links 116 may provide more functionality particularly in a multi-protocol multi-shelf network node deployment.
For example, due to the current market-driven necessity to consolidate voice and data communications, each control services link 116 may include an E1/T1 trunk. E1/T1 trunks are typically used for Time Division Multiplexed (TDM) transmission of digitized voice samples and voice communications control information in telephone networks. E1/T1-based transmissions adhere to a TDM frame format having frame markers recurring at an 8 kHz rate such that voice sample data corresponding to a particular service-level connection is found in the same bit position with respect to the frame marker. The standardized intended use of the Bellcore Stratum-3 compliant 8 kHz SSYNC signal relates directly to E1/T1 frame marker generation and detection—the analog characteristics of the frame marker being used in clock synchronization.
Whereas dedicated clock pins are employed by each interface card connector, and dedicated clock signal traces are employed on the backplane of a single shelf network node, a problem exists in respect of multi-shelf network node implementations 100 in bringing all clock signals derived from external communications links connected to physical ports associated with all peripheral shelves 106 to the SSU on the control card 112 of the control shelf 102, as a reference master clock signal, to synchronize content conveyance in the multi-shelf network node 100 thereto. For this reason, in a typical multi-shelf system 100 only master clock signals received via interface (line) cards (118) physically connected to the control shelf 102 can be used for content transport synchronization thereto. In the field, this restriction is seen as a hindrance in engineering and deploying communications networks employing multi-shelf network nodes 100.
There therefore is a need to solve the above mentioned issues.